1. Field of the Invention
The present invention relates to a 3D stacked NAND flash memory array and operation method thereof, and more particularly to a 3D stacked NAND flash memory array enabling a layer selection by multi-level operation (LSM), which gets rid of the waste of unnecessary areas by minimizing an increase in the number of string selection lines (SSLs) though vertically stacked layers are increased, and to an operation method of the same array.
2. Description of the Related Art
Recently, the utilization of flash memories as high integrity mass storage devices has been increasing, but there has been difficult in improving the degree of integrity under 20 nm due to limitation of the photolithography technology. So, various NAND flash memory arrays enabling three-dimensional (3D) stack have been studied.
When the memory structure having a 3D stacked shape is compared with the conventional two-dimensional (2D) planar structure, the greatest difference is a necessity of a layer selection in the 3D stacked memory structure during operation.
These days, the various 3D structures enabling a layer selection in the operation of writing (a program) and reading (a read) are being studied. One example is a 3D NAND flash memory array distinguishing stacked layers from each other by electrical erases 52 described in FIG. 1 and Korean Publication No. 10-2011-0111166.
The prior art is known as a structure performing a layer selection by erase operation (LASER). According to this structure, each SSL (LSL shown in FIG. 1 of Korean Publication No. 10-2011-0111166 is equal to SSL) and a body of an active line separately formed by each layer are used to extract electrons from a specific charge storage layer between the SSL and the body of the active line in each layer for electrically forming an erase state combination, namely an initialized state combination, instead of the impurity-doped layer combination physically formed in the conventional Korean Patent No. 10-1036155. So, it has merits that the layer selection can be more easily performed.
However, because the LASER structure, as shown in FIG. 2, is consisted of string selection transistors formed at locations crossed between each SSL and an active line (each layer of bit lines) and simply divided into initialized transistors (the transistors enclosed with a broken line in FIG. 2) and not, there have been some limitations in improving the degree of integrity by minimizing the number of SSLs for a layer selection.
When n is the number of SSLs and r is the number of initialized string selection transistors formed in each active line, the number of vertically stacked layers to be selected is equal to a combination expressed as nCr. To obtain the maximum value of nCr, r has to be the closest natural number to the middle value of n.
Therefore, the LASER structure, as shown in FIG. 2, needs 5 SSLs for selecting 10 layers and also shows that the more the number of layers increases, the more the number of SSLs is needed. Considering that the general width of SSL, i.e., the gate length of a string selection transistor, is 4-5 times larger than that of a memory cell gate (the width of a word line in FIG. 1) to overcome some problems such as a leakage current, short channel effect, etc., there has been gradually rising necessity to maximally and effectively restrain the increase in the number of required SSLs though the number of vertically stacked layers is increased.